1. Field of the Invention
The present invention is generally directed to a method and system for screening nets of circuit design in a post-layout environment. More specifically, the present invention is directed to a method and system operable during design verification for quickly and conveniently screening routed nets of a circuit layout, such as in a printed circuit board design, for potentially faulty nets warranting further evaluation.
2. Description of the Related Art
Typically, when a board level circuit layout has been designed (all circuit elements, including devices, discrete components, conductive traces, and the like have been placed and routed), it undergoes post-layout test/verification using a simulation tool.
The circuit layout at this stage defines a collection of nets, each forming a connection directly between circuit component pins. One or more nets are encompassed by a signal transmitting channel extending to include all passive circuit elements between a driver circuit element (which models a source for a signal) and a receiver circuit element (which models a destination for the signal). A typical circuit layout will easily include thousands of such nets, even hundreds of thousands; yet, adequate verification cannot be had without the reliable identification and remedy of individual nets having faults.
This is important for high speed circuit board applications, where point-to-point connections for transmitting signals cannot be treated simply as ideal short circuits. The distortion that signals experience during transmission between source and destination are hardly negligible in high speed applications, and individual nets of a circuit layout tend to behave much like distributed transmission lines having certain properties, each applying its own intrinsic attenuation and delay on the high speed signals passing therethrough.
For example, a signal originating with an amplitude of 5V at a driver element may arrive at the receiver with an amplitude of 4V due to signal loss through the transmission line. The signal may also be delayed during passage through the line by a non-negligible amount, say on the order of a nanosecond or so. If a high state transition voltage threshold of the receiver were 4.5V in that case, the receiver would erroneously take this signal to be of low voltage state (logic 0), though it had originated from the source as a 5V high state signal (logic 1). Consequently, the receiver would fail to recognize the intended high state signal as such (as it is below the threshold of 4.5 volts at the given point in time).
The potential for this kind of failure even in one individual net must be reliably ascertained during post-layout verification. Obviously, it is important that signals traversing the nets reach the respective receivers at their intended states, and arrive at the expected times. For certain signals, like signals on different nets of a data bus, for instance, where a byte or more of data is simultaneously sent each from multiple driving input/output (I/O) buffers, the delay factor is particularly important since all the bytes must reach the receiving end almost simultaneously. Pervasive timing problems are generated if they are out of phase. Hence, signal channel quality must be preserved for each net to guard sufficiently against the effects of noise and to maintain proper signal timing.
This presents a formidable challenge in applications where thousands of nets are presented for verification of a circuit layout, any one of which could potentially be of problematic signal channel quality. With the post-layout verification tools heretofore known, a full blown simulation analysis is performed on virtually all the nets in order to identify the problematic ones. This process is excessively complex and time consuming, and involves process-intensive simulation runs using many bits. Except in limited applications, the costs in this regard tend to be prohibitively expensive, and sufficiently expansive testing for faulty nets is often impracticable.
There is therefore a need for a method and system whereby potentially faulty, or problematic, nets of a circuit layout may be quickly and conveniently screened for without the need for comprehensive, processing-intensive, and resource-consuming simulation analysis. There is a need for such system and method by which the signal channel quality of the circuit layout's nets may be readily ascertained and compared, so that available time and resources may be committed to closer scrutiny and remedy of signal channels which are actually problematic, rather than being wasted on already acceptable signal channels.